1. Technical Field
The present disclosure relates to a transmitter. Particularly, embodiments of the present disclosure relate to a transmitter capable of reducing power consumption by reducing a swing width of a transmission signal.
2. Related Art
FIG. 1 is a circuit diagram of a conventional transmitter.
The conventional transmitter includes a driving circuit 1 and a driving signal generation circuit 2.
The driving circuit 1 outputs an output signal VO, which swings between a power supply voltage VDD and a ground voltage VSS, in response to a driving control signal outputted from the driving signal generation circuit 2.
The driving circuit 1 includes a PMOS transistor P0 and an NMOS transistor NO, which have drains commonly coupled to each other. The output signal VO is outputted from the commonly coupled drains.
The power supply voltage VDD is provided to a source of the PMOS transistor P0 and the ground voltage VSS is provided to a source of the NMOS transistor NO.
The driving signal generation circuit 2 includes a NAND gate ND1 that performs a NAND operation on a data signal D and an activation signal EN to control a gate of the PMOS transistor P0, an inverter INV0 that inverts the activation signal EN, and a NOR gate NR1 that performs a NOR operation on an output signal of the inverter INV0 and the data signal D to control a gate of the NMOS transistor N0.
When the activation signal EN has a logic low level, since an output signal of the NAND gate ND1 has a logic high level and an output signal of the NOR gate NR1 has a logic low level, the PMOS transistor P0 and the NMOS transistor NO are turned off and the output signal VO is in a floating state.
When the activation signal EN has a logic high level, if the data signal D has a logic high level, the output signal of the NAND gate ND1 and the output signal of the NOR gate NR1 respectively become to have a logic low level. Accordingly, the PMOS transistor P0 is turned on and the NMOS transistor NO is turned off. As a result, the output signal VO has the power supply voltage VDD.
On the other hand, when the activation signal EN has the logic high level, if the data signal D has a logic low level, the output signal of the NAND gate ND1 and the output signal of the NOR gate NR1 respectively become to have a logic high level. Accordingly, the PMOS transistor P0 is turned off and the NMOS transistor NO is turned on. As a result, the output signal VO has the ground voltage VSS.
As described above, in the conventional transmitter, since the output signal VO fully swings between the power supply voltage VDD and the ground voltage VSS, power consumption may be significant due to the full switching operation of the transmitter.